Bio: Ljiljana Trajkovic
received the Dipl. Ing. degree from University of Pristina,
Yugoslavia, the M.Sc. degrees in electrical engineering and
computer engineering from Syracuse University, Syracuse, NY, and
the Ph.D. degree in electrical engineering from University of
California at Los Angeles. She is currently a professor in the
School of Engineering Science, Simon Fraser University, Burnaby,
British Columbia, Canada. Her research interests include
communication networks and dynamical systems. She served as IEEE
Division X Delegate/Director, President of the IEEE Systems, Man,
and Cybernetics Society, and President of the IEEE Circuits and
Systems Society. Dr. Trajkovic serves as Editor-in-Chief of the
IEEE Transactions on Human-Machine Systems and Associate
Editor-in-Chief of the IEEE Open Journal of Systems Engineering.
She served as a Distinguished Lecturer of the IEEE Circuits and
System Society and a Distinguished Lecturer of the IEEE Systems,
Man, and Cybernetics Society. She is a Fellow of the IEEE.
Speech Title: Machine Learning for Detecting
Internet Traffic Anomalies
Abstract:
Border Gateway Protocol (BGP) enables the Internet data routing.
BGP anomalies may affect the Internet connectivity and cause
routing disconnections, route flaps, and oscillations. Hence,
detection of anomalous BGP routing dynamics is a topic of great
interest in cybersecurity. Various anomaly and intrusion detection
approaches based on machine learning have been employed to analyze
BGP update messages collected from RIPE and Route Views collection
sites. Survey of supervised and semi-supervised machine learning
algorithms for detecting BGP anomalies and intrusions is
presented. Deep learning, broad learning, gradient boosting
decision tree, and reservoir computing algorithms are evaluated by
developing models based on collected datasets that contain
Internet worms, power outages, and ransomware events.
Bio: Xiaoqing WEN received a
B.E. degree from Tsinghua University, China, in 1986, a M.E.
degree from Hiroshima University, Japan, in 1990, and a Ph.D.
degree from Osaka University, Japan, in 1993. He was an Assistant
Professor with Akita University, Japan, frrom 1993 to 1997, and a
Visiting Researcher with the University of Wisconsin–Madison, USA,
from Oct. 1995 to Mar. 1996. He joined SynTest Technologies Inc.,
USA, in 1998, and served as its Vice President and Chief
Technology Officer until 2003. He joined Kyushu Institute of
Technology, Japan, in 2003, where he is currently a Professor of
the Department of Computer Science and Networks. He founded
Dependable Integarted Systems Research Center at Kyushu Institute
of Technology in 2013 and served as its Director until 2015. He is
a Co-Founder and Co-Chair of Technical Activity Committee on
Power-Aware Testing under Test Technology Technical Council (TTTC)
of IEEE Computer Society. He is an Associate Editor for IEEE
Transactions on Very Large Scale Integration Systems (TVLSI) and
Journal of Electronic Testing: Theory and Applications (JETTA). He
co-authored and co-edited two popular books, VLSI Test Principles
and Architectures: Design for Testability (2006) and Power-Aware
Testing and Test Strategies for Low Power Devices (2009). His
research interests include design, test, and diagnosis of VLSI
circuits. He holds 43 U.S. Patents and 14 Japan Patents. He
received the 2008 Society Best Paper Award from the Infromation
Systmes Society (ISS) of the Institute of Electronics, Information
and Communication Engineers (IEICE). He is a Fellow of IEEE for
his pionerring work in low capture power test generation, a Senior
Member of Information Processing Society of Japan (IPSJ), and a
Senior Member of IEICE.
Speech Title: LSI Testing: A Core Technology to a
Successful Semiconductor Industry
Abstract:
The semiconductor industry is exposed to shrinking feature sizes,
growing circuit complexity, increasing clock speeds, and
decreasing power supply voltages. In addition to significant
impact on LSI design and manufacturing, these factors also have a
profound impact on LSI testing, a complex process for separating
defective chips from defect-free ones. The major challenges to LSI
testing are low test quality, high test cost, and excessive test
power. These challenges have led to new chances of innovations in
LSI testing, characterized by cell-aware test generation, test
compression, and power-aware testing. This talk will review these
challenges and chances. Furthermore, this talk will reveal the
role of LSI testing in the semiconductor business chain, so as to
explain why LSI testing is a core technology to a successful
semiconductor industry.